1. Field of the Invention
The present invention relates in general to the field of electronics, and more specifically to a system and method for sensing switch controlled currents using a Hall effect sensor.
2. Description of the Related Art
Electronic systems often detect signal values and utilize the values to perform other operations. Hall effect sensors (“Hall sensors”) are used in some contexts to detect signals. A Hall sensor generates a voltage corresponding to a magnetic field passing through the Hall sensor. An electrical current flowing through a conductor in proximity to a Hall sensor generates a magnetic field. The Hall sensor generates a voltage corresponding to the magnetic field generated by the current. Hall sensors generally have a low frequency noise component that is too large to allow detection of small changes in currents. For example, as explained subsequently in more detail, switching power converters that operate in continuous conduction mode (CCM) sense currents using a current sense circuit such as a resistor or a transformer.
FIG. 1A represents a power control system 100, which includes switching power converter 102. In at least one embodiment, switching power converter operates in a continuous conduction mode (CCM). In CCM, the inductor current iL does not go to zero during operation of switching power converter 102. As subsequently described in more detail, in CCM operation, PFC and output voltage controller 114 senses controlled current iCC by sensing a voltage across resistor 109. Voltage source 101 supplies an alternating current (AC) input voltage VIN to a full bridge diode rectifier 103. The voltage source 101 is, for example, a public utility, and the AC voltage VIN is, for example, a 60 Hz/110 V line voltage in the United States of America or a 50 Hz/220 V line voltage in Europe. The rectifier 103 rectifies the input voltage VIN and supplies a rectified, time-varying, line input voltage VX to the switching power converter.
The switching power converter 102 includes at least two switching operations, i.e. controlling field effect transistor (FET) 108 to provide power factor correction and controlling FET 108 to provide regulation of link voltage VLINK. The goal of power factor correction technology is to make the switching power converter 102 appear resistive to the voltage source 101 so that the real power provided to switching power converter 102 is equal to the apparent power provided to switching power converter 102. The inductor current iL ramps ‘up’ when FET 108 conducts, i.e. is “ON”. The inductor current iL ramps down when FET 108 is nonconductive, i.e. is “OFF”, and supplies current iL to recharge capacitor 106. The time period during which inductor current iL ramps down is commonly referred to as the “inductor flyback time”. Diode 111 prevents reverse current flow into inductor 110. In at least one embodiment, control signal CS0 is a pulse width modulated signal, and FET 108 is an n-channel FET. In this embodiment, control signal CS0 is a gate voltage of FET 108, and FET 108 conducts when the pulse width of CS0 is high. Thus, the ‘on-time’ of FET 108 is determined by the pulse width of control signal CS0. In at least one embodiment, the switching power converter 102 operates in CCM, i.e. ramp up time of the inductor current iL plus the inductor flyback time is greater than or equal to the period of the control signal CS0.
In at least one embodiment, switching power converter 102 boosts a 110-120 V rectified input voltage VX to a higher link voltage VLINK, such as 200-400V. Accordingly, FET 108 is fabricated to have a breakdown voltage sufficient to accommodate the controlled current iCCT and voltage drops across FET 108 associated with the high input voltage VX and higher link voltage VLINK. FET 108 is a high breakdown voltage device fabricated using a “high” voltage process. In at least one embodiment, FET 108 has a breakdown voltage greater than or equal to 30V and at least sufficient to accommodate operating characteristics of switching power converter 102. In at least one embodiment, power factor correction (PFC) and output voltage controller 114 is an integrated circuit and is fabricated using a low voltage process that is insufficient to fabricate a switch with a sufficiently high breakdown voltage to control the controlled current iCCT. Thus, FET 108 is located external to PFC and output voltage controller 114. As subsequently described in more detail, PFC and output voltage controller 114 generates a pulse width modulated control signal CS0 to control conductivity of FET 108. In at least one embodiment, FET 108 is a FET, and control signal CS0 is a gate voltage.
Switching power converter 102 includes current sense resistor 109. The switch controlled current iCC generates a sense voltage VSEN across current sense resistor 109. The PFC and output voltage controller 114 receives the sense voltage VSEN. The resistance R of sense resistor 109 is known. The sense voltage VSEN is directly related to switch controlled current iCC via Ohm's law, i.e. VSEN=iCC·R. “R” represents a resistance value of sense resistor 109, and the value of R is a matter of design choice. In at least one embodiment, PFC and output voltage controller 114 utilizes the sense voltage VSEN and sensing two signals, namely, the line input voltage VX and the capacitor voltage/output voltage VLINK to generate the pulse width and duty cycle of control signal CS0.
Capacitor 106 supplies stored energy to load 112. The capacitor 106 is sufficiently large so as to maintain a substantially constant output voltage VLINK, as established by PFC and output voltage controller 114 (as discussed in more detail below). The output voltage VLINK remains substantially constant during constant load conditions. However, as load conditions change, the output voltage VLINK changes. The switch state controller 114 responds to the changes in VLINK and adjusts the control signal CS0 to restore a substantially constant output voltage as quickly as possible. The PFC and output voltage controller 114 includes a small capacitor 115 to filter any high frequency signals from the line input voltage VX.
The switch state controller 114 of power control system 100 controls FET 108 and, thus, controls power factor correction (PFC) and regulates output power of the switching power converter 102. As previously stated, the goal of power factor correction technology is to make the switching power converter 102 appear resistive to the voltage source 101. Thus, the switch state controller 114 attempts to control the inductor current iL so that the average inductor current iL is linearly and directly related to the line input voltage VX. A CCM PFC controller, model number UCC28019A, available from Texas Instruments, Inc., Texas, USA is an example of switch state controller 114. The switch state controller 114 controls the pulse width (PW) and period (TT) of control signal CS0. To regulate the amount of energy transferred and maintain a power factor close to one, switch state controller 114 varies the period of control signal CS0 so that the input current iL tracks the changes in input voltage VX and holds the output voltage VLINK constant. Thus, as the input voltage VX increases, switch state controller 114 increases the period TT of control signal CS0, and as the input voltage VX decreases, switch state controller 114 decreases the period of control signal CS0. At the same time, the pulse width PW of control signal CS0 is adjusted to maintain a constant duty cycle (D) of control signal CS0, and, thus, hold the output voltage VLINK constant.
In at least one embodiment, the switch state controller 114 updates the control signal CS0 at a frequency much greater than the frequency of input voltage VX. The frequency of input voltage VX is generally 50-60 Hz. The frequency 1/TT of control signal CS0 is, for example, between 20 kHz and 130 kHz. Frequencies at or above 20 kHz avoid audio frequencies and frequencies at or below 130 kHz avoid significant switching inefficiencies while still maintaining good power factor, e.g. between 0.9 and 1, and an approximately constant output voltage VLINK.
Light emitting diodes (LEDs) are becoming particularly attractive as main stream light sources in part because of energy savings through high efficiency light output and environmental incentives such as the reduction of mercury. LEDs are semiconductor devices and are driven by direct current. The brightness (i.e. luminous intensity) of the LED approximately varies in direct proportion to the current flowing through the LED. Thus, increasing current supplied to an LED increases the brightness of the LED and decreasing current supplied to the LED dims the LED. Current can be modified by either directly reducing the direct current level to the LEDs or by reducing the average current through the LEDs through duty cycle modulation.
FIG. 1B depicts an LED driver system 150. The LED driver system 150 includes a CCM, buck-based switching power converter 152 to provide a load voltage to switching LED system 154. Voltage source 151 supplies the AC supply voltage VIN to a full, diode bridge rectifier 153. The hold-up capacitor C1 holds an approximately direct current (DC) link voltage VLINK across capacitor C1 relative to a reference voltage VR. Link voltage VLINK is also the output voltage of power converter 152 and the input voltage for controller 156. Input filter capacitor C2 provides a high pass filter for high frequency components of the output voltage of rectifier 153. A thermistor NTC1 provides in-rush current protection for power converter 152.
The controller 156 is, for example, a Supertex HV9915B integrated circuit controller available from Supertex, Inc. of Sunnyvale, Calif. The link voltage VLINK can vary from, for example, 8V to 450V. The controller 156 provides a gate drive signal from the GATE output node to the n-channel metal oxide semiconductor field effect transistor (MOSFET) Q1. Controller 156 modulates the gate drive signal, and thus, the conductivity of MOSFET Q1 to provide a constant current to LED system 154. Controller 156 modifies the average resistance of MOSFET Q1 by varying a duty cycle of a pulse width modulated gate drive signal VGATE. Resistor R1 and capacitor C3 provide external connections for controller 156 to the ground reference.
Controller 156 generates and uses feedback to maintain a constant current iLED for LEDs 158. Controller 156 receives a current feedback signal Vfb representing a feedback voltage Vfb sensed across sense resistor R2. The feedback voltage Vfb is directly proportional to the LED current iLED in LEDs 158. If the feedback voltage Vfb exceeds a predetermined reference corresponding to a desired LED current, the controller 156 responds to the feedback voltage Vfb by decreasing the duty cycle of gate drive signal VGATE to increase the average resistance of MOSFET Q1 over time. If the feedback voltage Vfb is less than a predetermined reference corresponding to the desired LED current, the controller 156 responds to the feedback voltage Vfb by increasing the duty cycle of gate drive signal VGATE to decrease the average resistance of MOSFET Q1 over time.
The LED system 154 includes a chain of one or more, serially connected LEDs 158. When the MOSFET Q1 is “on”, i.e. conductive, diode D1 is reversed bias and, current iLED flows through the LEDs 158 and charges inductor L1. When the MOSFET Q1 is “off”, i.e. nonconductive, the voltage across inductor L1 changes polarity, and diode D1 creates a current path for the LED current iLED. The inductor L1 is chosen so as to store enough energy to maintain a constant current iLED when MOSFET Q1 is “off”.
Sensing the controlled current through current sense circuit 109 (FIG. 1A) and the controlled LED current iLED through resistor R2 (FIG. 1B) results in power loss and can be inaccurate.